The Design and Implementation of High Performance Multiplier Unit on DSP Chip Archive - IT Research Paper

The Design and Implementation of High Performance Multiplier Unit on DSP Chip

Title The Design and Implementation of High Performance Multiplier Unit on DSP Chip
Abstract

For DSPs dealing with operations such as convolution, filtering, FFT which consist of repeated additions and multiplications, a multiplier handling the work fast and efficiently becomes a key role. What’s more, the number of multiply-add operations a DSP can achieve per second is one of the most important indices evaluating the performance. The model XDSP, a fixed 32-bit one, which is now under research, is planned to reach the frequency of 600MHz and 4800 million MAC per second after tapped out. Thus, a high performance multiplier is indispensable.This thesis mainly designs a multiplier, a functional unit of XDSP. Full custom designs of a SIMD multiplier and a configurable finite field multiplier are protagonists.Due to SIMD algorithm improvement, a two-mode multiplier is proposed that can dynamically adjust to the execution of different instructions, i.e. normal multiplication and SIMD multiplication, either pipelined or in a single period, eliminating constraints and faults of the architecture such as combining sub-word or simple parallel way. MBE and a good policy of the generation of partial products make this multiplier half of a array parallel one in area and 80% in power dissipation. Simulations show that, the two–stage pipelined SIMD multiplier can accomplish one 32×16 or two 16×16 or four 8×8 multiplications at a frequency of 600MHz.A multiplier with variable field and primitive polynomials is advanced employing polynomial-independent algorithm and complementary field conversion logic. The multiplier, a regular complementary static CMOS LSB first semi-systolic array, achieving a high speed while maintaining low power dissipation, can work steadily as fast as 800MHz under a four-stage pipeline. It gains advantage over present mono-function ones.

Category Internet
Keywords Booth, DSP, finite field, multiplier, Semi-systolic Array, SIMD,
FileType PDF
Pages 174
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