Posts Tagged ‘LDPC decoder’:

On the FPGA Design and Implementation of the IEEE802.16e LDPC Decoder

Since being rediscovered in 1990s, LDPC codes have attracted people’s attention and have become another research focus of channel coding filed after Turbo codes because of their capacity approaching error correction capability and the advantages of low decoding complexity and high decoding throughput. Today, LDPC codes have been widely applied in different communication systems such

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Research on Quasi-Cyclic Low-Density Parity-Check Codes

Low-density parity-check codes are a class of linear block codes which approach Shannon limit. With the development of LDPC encoder/decoder design and research, Quasi-cyclic (QC) LDPC codes are widely studied for their comparable performance and hardware-friendly characteristic. This thesis first introduces the principles of finite field LDPC codes, and then focuses on the construction of

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Analysis and Simulation of Encode and Decode of LDPC Code in DVB-S2 Standard

LDPC code is a type of error correcting block code with very sparse check matrix which was first proposed by Gallager in the early 1962. But because of the technology, it was scarcely considered in the 35 years that followed. The study of LDPC code was resurrected with the work of Mackay and others. They

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